1. Field of the Invention
The invention relates to an electrically erasable programmable non-volatile semiconductor memory device (EEPROM), such as a flash memory, etc.
2. Description of the Related Art
A highly integrated NAND-type non-volatile semiconductor memory device (refer to Patent Documents 1-4) well known in the art connects a plurality of memory cell transistors (hereinafter referred to as memory cells) to and between bit lines and source lines in series, so as to form a NAND string.
For a common NAND-type non-volatile semiconductor memory device, when erasing is performed, a high voltage, such as 20V, is applied to a semiconductor substrate thereof and 0V is applied to a word line thereof. As such, electrons are pulled out from a floating gate, i.e., the charge accumulation layer formed by poly-silicon material etc. and, the threshold voltage is lower than the erasing threshold voltage (for example, −3V). In addition, when write-in (programming) is performed, 0V is applied to the semiconductor substrate and a high voltage, such as 20V, is applied to a controlling gate. As a result, electrons are injected from the semiconductor substrate into the floating gate, thereby making the threshold voltage higher than the write-in threshold voltage (for example, 1V). The state of the memory cell which utilizes the threshold voltages may be determined by applying a readout voltage between the write-in threshold voltage and the readout threshold voltage (for example, 0V) to the control gate to determine whether a current is flowing thereto.
However, with the NAND-type flash memory having characteristics of low operating voltage and high density, coupling noise induced by the capacitance between the read bit lines must be addressed. According, a bit line shielding technology (for example, refer to Patent Document 1) is provided to solve the above-mentioned problem, thereby reducing coupling noise between the bit lines. According to the bit line shield technology, when reading pages, every other bit line is readout and the unselected bit lines are grounded. That is, the selected cell and unselected cell are connected to each other to form a control gate line.
In addition, Patent Document 5 illustrates how electrical characteristics of non-volatile memory, such as a flash memory, etc, may be improved and has the following structure. Wiring (signal wiring), forms the first layer of wiring layers. Selection gate transistors are formed in the area of a memory matrix, and the signal wiring is formed on the top of the area of the selection gate transistors. Next, in the area of the memory matrix, shielding wiring is formed in the non-wire area where no signal wiring is present. That is, the shielding wiring is formed on the top of the memory cell matrix area which does not form signal wiring. A global bit line is formed at a second layer of the wiring layers for commonly connecting to a plurality of the bit lines. The shielding wiring formed at the first layer is used to shield the global bit line at the second layer and reduce coupling noise between adjacent global bit lines.    [Patent Document 1] JP H09-147582.    [Patent Document 2] JP 2000-285692.    [Patent Document 3] JP 2003-346485.    [Patent Document 4] JP 2001-028575.    [Patent Document 5] JP 2007-123652.    [Non-Patent Document 1] Tomoharu Tanaka et al., “A Quick Intelligent Page-Programming Architecture and a Shielded Bitline Sensing Method for 3 V-only NAND Flash Memory”, IEEE Journal of Solid-State Circuits, Vol. 29, No. 11, pp. 1366-1373, November 1994.
In the bit line shielding technology as illustrated in non-Patent Document 1, every other global bit line is grounded to function as a shielding line during reading/verifying of the NAND-type flash memory. Generally, noise between adjacent bit lines may be prevented when data is read on the global bit line. Transistors for connecting the global bit line to the ground are arranged at a near terminal, or arranged at the near terminal and a far terminal (both terminals of the global bit line) of a page buffer.
The impedance of a global bit line and the capacitance between adjacent bit lines increase along with miniaturization. Meanwhile, the distant ground transistor may attenuate the shielding effectiveness in the middle of the global bit line. As such, it is necessary to divide the global bit line to maintain shielding effectiveness. Thus, an additional page buffer row is necessary due to the division of the global bit line. Accordingly, chip size and chip cost is increased. A detailed description is given as below.
FIG. 10 is a schematic diagram illustrating ground transistor parts 10A and 10B of a memory cell array according to the prior art. Further, FIG. 11 is a timing diagram illustrating the operation of the circuit as shown in FIG. 10. Referring to FIG. 10, ground transistors 21 and 22 are respectively disposed on the ground transistors parts 10A and 10B on two terminals of a global bit line GBL. Cc indicates the capacitance of adjacent global bit lines GBL. As shown in FIG. 11, SGBL indicates a global bit line which is shielded and not read, DGBL indicates a reading global bit line where charges have been discharged from the memory cell and NDGBL indicates a reading global bit line where charges have not been discharged from the memory cell.
Referring to FIG. 10, for example, when a NAND string connected to the point Pb is discharged through a global bit line GBL, coupling noise may overlap on the line between the point Pb and the point Pd of adjacent global bit lines GBL and may even further be transmitted to the line between the point Pe and the point Pf of the adjacent global bit lines GBL. As a result, the line between the point Pe and the point Pf of the adjacent global bit lines GBL is affected. When reading a NAND string which has not been discharged, a drop in voltage of the bit line due to substantially large noise may undesirably result in misreading, as shown in 101 of FIG. 11.
FIG. 12 is a schematic diagram illustrating the ground transistor parts 10A and 10B of another memory cell array according to the prior art. As shown in FIG. 12, in order to mitigate the aforementioned problem, the length of the global bit line GBL is divided by 2 and a page buffer 14 is disposed in the middle. Although the impedance of the global bit line GBL is reduced by half, a problem of an increased chip size may occur.